The present invention relates to a device structure of a semiconductor device (or semiconductor integrated circuit device) or a technology effective when applied to a memory structure and a wiring technology in the manufacturing method of a semiconductor device (or a semiconductor integrated circuit device).
Japanese Patent Laid-Open No. 2004-363411 (Patent Document 1) and U.S. Patent Laid-Open No. 2005-30821 (Patent Document 2) corresponding thereto disclose a technology of providing, in a semiconductor integrated circuit device having an MRAM (magnetic random access memory) cell portion and a peripheral circuit, a clad layer only for a write word line adjacent to the lower portion of an MTJ (magnetic tunnel junction) element of the MRAM cell portion and thereby preventing wiring layers from becoming complex in the peripheral circuit.
Japanese Patent Laid-Open No. 2005-294723 (Patent Document 3) discloses a technology of, in a semiconductor integrated circuit device having an MRAM cell portion and a peripheral circuit, providing a structure in which only a lower-level wiring configuring a write word line and a bit line adjacent to the top and bottom of an MTJ element in the MRAM cell portion has a clad layer and using wirings located above them in the peripheral circuit, thereby preventing the wiring layers from becoming complex in the peripheral circuit.
Japanese Patent Laid-Open No. 2008-205119 (Patent Document 4) or U.S. Patent Laid-Open No. 2008-197496 (Patent Document 5) corresponding thereto discloses a copper-embedded wiring added with aluminum or the like as a measure against EM (electromigration) and SM (stress migration).